The present invention relates to power semiconductor devices.
Power metal oxide semiconductor (MOS) transistors and insulated gate bipolar transistors (IGBTs) can be grouped as either enhancement-mode or depletion-mode devices. Depletion-mode devices inherently include a pair of P/N junctions that form a parasitic bipolar transistor. Generally, it is preferable to prevent the parasitic transistor from being turned on during operation of the power devices, so that the switching speed of the device is not degraded. Also, if the parasitic transistor does turn on, the primary bipolar device may become latched in the on state that may result in destruction of the device.
As used herein, the term “power device” or “power semiconductor device” refers to the power MOS transistor, an IGBT, or other power switching devices.
Attempts have been made to minimize the likelihood of turning on the parasitic transistor. One method has been to short the source electrode of the MOS device to the body region of the device. This effectively shorts the base and emitter of the parasitic transistor together at the surface of the device. However, because of series resistance in the device body, other portions of the base and emitter are not shorted but have a relatively high impedance bridging the two elements. A highly doped region can be added to reduce the effective resistance of the bridging impedance. Another method has been to provide a resistive path between a source contact area and a channel section to provide a ballast voltage, e.g., U.S. Pat. No. 4,860,072, which is incorporated by reference herein for all purposes.